Field of the Invention
The invention relates to a package substrate and a manufacturing method thereof, and relates particularly to a coreless package substrate and a manufacturing method thereof.
Description of Related Art
In a semiconductor manufacturing process, a chip packaging substrate is one of the basic building blocks of packaging components. The chip packaging substrate, for example, may be a single-layer circuit board, a two-layer circuit board or a multi-layer circuit board which is constituted by alternatively stacking a plurality of circuit layers and a plurality of dielectric layers. In general, the circuit layers and the dielectric layers in the multi-layer circuit board are built up on a core substrate with a certain thickness. Along with the development of thin electronic components, the thickness of the core substrate is reduced accordingly. However, with the reduction in the thickness of the core substrate, the degree of difficulty in handling, the failure rate of the substrate manufacturing process and the packaging process all increase due to insufficient rigidity of the thin core substrate.
Hence, by using the coreless process in the manufacturing of the multi-layer circuit board, the problems arising in the substrate and the packaging process can be solved. In the coreless process, the core substrate is not used. A carrier panel serves as a temporary support to form build-up circuit layers thereon. After the multi-layer circuit board is completed, it is separated from the carrier. In the conventional coreless process, a part of the edges of the carrier and a part of the edges of the multi-layer circuit board are bonded together. After the manufacturing processes are completed (e.g., etching, circuit lamination, or laser drill), the edges of the carrier bonded with the multi-layer circuit board are routed out leaving the multi-layer circuit board without the edge areas for the subsequent processes. However, when a thickness of the package substrate becomes thinner, in the conventional coreless process, relative movements are easily produced during the manufacturing processes since the carrier and the multi-layer circuit board are only bonded together at particular parts, or deformation is produced at parts where the carrier and the multi-layer circuit are not bonded, further increasing the failure rate of the coreless manufacturing process. How to provide a stable temporary carrier and increase the yield of the manufacturing process and the subsequent separation process is a problem needing to be solved.